J Mater Sci Technol ›› 2009, Vol. 25 ›› Issue (03): 289-313.

• Reviews •     Next Articles

Challenges in Atomic-Scale Characterization of High-k Dielectrics and Metal Gate Electrodes for Advanced CMOS Gate Stacks

Xinhua Zhu, Jian-min Zhu, Aidong Li, Zhiguo Liu, Naiben Ming   

  • Received:2008-02-02 Online:2009-05-28 Published:2009-10-10
  • Supported by:

    Natural Science Foundation of Jiangsu Province (Project No. BK2007130),
    National Natural Science Foundation of China (Grant Nos. 10874065, 60576023 and 60636010),
    Ministry of Science and Technology of China (Grant No. 2009CB929503),
    key projects from Ministry of Science and Technology of China (Grant Nos. 2009CB929503 and 2009ZX02101-4),
    the project sponsored by the Scientific Research Foundation for the Returned Overseas Chinese Scholars,
    State Education Ministry, and National Found for Fostering Talents of Basic Science (NFFTBS) (Project No. J0630316).

Abstract:

The decreasing feature sizes in complementary metal-oxide semiconductor (CMOS) transistor technology will require the replacement of SiO2 with gate dielectrics that have a high dielectric constant (high-k) because as the SiO2 gate thickness is reduced below 1.4 nm, electron tunnelling effects and high leakage currents occur in SiO2, which present serious obstacles to future device reliability. In recent years significant progress has been made on the screening and selection of high-k gate dielectrics, understanding their physical properties, and their integration into CMOS technology. Now the family of hafnium oxide-based materials has emerged as the leading candidate for high-k gate dielectrics due to their excellent physical properties. It is also realized that the high-k oxides must be implemented in conjunction with metal gate electrodes to get sufficient potential for CMOS continue scaling. In the advanced nanoscale Si-based CMOS devices, the composition and thickness of interfacial layers in the gate stacks determine the critical performance of devices. To build up a full atomic-scale understanding of high-k gate stacks, including their ultimate electrical properties, a thorough atomic-scale physical analysis of these ultrathin gate stacks are highly required. High-resolution microscopic and spectroscopic methods are central in facilitating high-k gate dielectrics to be integrated in CMOS devices and to continue scaling. In this review, we summarize the strengths and capabilities of several high-resolution electron, ion, and photon-based techniques currently used to characterize the high-k gate dielectrics at atomic scale. Particularly, we review the enormous progresses on characterizing interface behavior and structural evolution in the high-k gate dielectrics by high-resolution transmission electron microscopy (HRTEM), and the related techniques based on scanning transmission electron microscopy (STEM), including high-angle annular dark-field (HAADF) imaging (also known as Z-contrast imaging), electron energy-loss spectroscopy (EELS), and energy dispersive X-ray spectroscopy (EDS). This review is organized into five sections. In the first section, we briefly introduce the working principles of each technique and outline their key features. And then we critically review the advances on microstructural characterization of high-k gate dielectrics at atomic scale by electron microscopy, citing some recent results reported on high

Key words: High-k gate dielectrics, Metal gate electrodes, CMOS gate stack, HRTEM, STEM