Abstract: Ferroelectric thin film transistors (FeTFTs) have attracted great attention for in-memory computing applications due to low power consumption and monolithic three-dimensional integration capability. Herein, we propose a planar integrated highly-reliable metal-ferroelectric-metal-insulator-semiconductor FeTFTs device, in which the weak erase issue is suppressed by implanting a floating gate, and the interface defects are reduced by simplifying the fabrication process. These lead to significant improvements in device performance, including large memory window (4.3 V), high conductance dynamic range (1400), high endurance (10¹²), and low variation (cycle-to-cycle: 2.5 %/device-to-device: 3.5 %). Moreover, we fabricated a 16 × 16 FeTFTs pseudo-crossbar array for in-memory computing and experimentally demonstrated full hardware implementation of multi-layer perceptron for the classification of four fundamental arithmetic operation symbols. This work provides a potential hardware solution for implementing a highly-efficient in-memory computing system based on highly-reliable FeTFTs array.

Key words: Ferroelectric, Thin-film transistors array, In-memory computing, Image classification