J. Mater. Sci. Technol. ›› 2022, Vol. 97: 254-263.DOI: 10.1016/j.jmst.2021.04.071
• Research Article • Previous Articles Next Articles
Nasir Ilyasa,c, Jingyong Wanga, Chunmei Lia, Hao Fuc,*(), Dongyang Lia, Xiangdong Jianga, Deen Gua, Yadong Jianga,b, Wei Lia,b,*(
)
Received:
2021-02-02
Revised:
2021-04-20
Accepted:
2021-04-22
Published:
2021-07-12
Online:
2021-07-12
Contact:
Hao Fu,Wei Li
About author:
wli@uestc.edu.cn (W. Li).Nasir Ilyas, Jingyong Wang, Chunmei Li, Hao Fu, Dongyang Li, Xiangdong Jiang, Deen Gu, Yadong Jiang, Wei Li. Controllable resistive switching of STO:Ag/SiO2-based memristor synapse for neuromorphic computing[J]. J. Mater. Sci. Technol., 2022, 97: 254-263.
Fig. 1. (A) Schematic model of the Ag/STO:Ag/SiO2/p++-Si memristor. (B) Cross-sectional TEM image of the Ag/STO:Ag/SiO2/p++-Si memristor. (C—H) TEM-EDS spectrum and elemental-mapping images of the region indicated by yellow square for Sr, Ti, Ag, O and Si, respectively.
Fig. 2. (A, D) I-V curves of Ag/SiO2/p++-Si and Ag/STO/p++-Si devices, respectively, the insets are the demonstrating structures differently. (B, C) Cumulative distribution of resistance values at HRS/LRS and histogram of Ag/SiO2/p++-Si device for set and reset of consecutive 100 sweep cycles drawn from Fig. S1. (E, F) Cumulative distribution of resistance values at HRS/LRS and histogram of Ag/STO/p++-Si device for set and reset of consecutive 100 sweep cycles drawn from Fig. S1.
Fig. 3. (A) I-V curves of Ag/STO:Ag/SiO2/p++-Si memristor, the inset shows the electroforming of Ag/STO/SiO2/p++-Si device. (B) Evolution of resistance values at HRS and LRS upto 5000 consecutive set/reset cycles. (C) I-V curves of the Ag/STO:Ag/SiO2/p++-Si device under different compliance currents. (D) Retention characteristics of 5 resistance states for over 103 s. (E, F) Cumulative distribution of HRS and LRS values and histograms of the reset/set operating voltage in 100 randomly selected devices.
Fig. 4. Schematic illustration, C-AFM current mapping images and I-V analysis in double logarithmic scale for physical mechanism involve in resistive switching behavior. (A) Pristine Ag/STO:Ag/SiO2/p++-Si memristor. (B, C) The electroforming (SET) and RESET by Ag atoms migrated from the top electrode to the bottom electrode and vice versa. (D-F) C-AFM current mapping images (read voltage: 0.5 V; SET voltage: 10 V; RESET voltage: -8.0 V). The insets show the profile lines of the current maps. The scanned area is 5 µm × 5 µm. (G, H) Fitting results for set and reset from replotted I-V curve in double logarithmic scale. (I) Temperature effect of LRS state and linear fitting of obtained data.
Fig. 5. (A) Device response, (B) endurance test result and (C) retention property under a pulsed stimulation mode. The device is stimulated by a pulse bias of height +3.0 V for set and -3.0 V for reset, and the response current is measured at +0.3 V.
Fig. 6. (A) Gradual set and (B) reset processes by repeated sweeping positive and negative voltage respectively, ranging from 1.6 V to 2.6 V with step voltage of 0.2 V. (C, D) Response to the pulses with +2.0 V for potentiation and -2.0 V for depression of the Ag/STO:Ag/SiO2/p++-Si device.
Fig. 7. (A) Schematic diagram of biological synapse and synaptic modulation between presynaptic and post-synapse with the migration of Ca2+ or K+ ions when an action potential is received. (B) Schematic diagram of STO:Ag/SiO2-based device and its conductance modulation at pulse bias stimulation. (C, D) PPF and fitting results of current response with pulse intervals. (E, F) Illustration of programming for pulse interval of 5 ms, 10 ms, 15 ms and 20 ms, and the current responses.
Fig. 8. The synaptic weight change (ΔW) of Ag/STO:Ag/SiO2/p++-Si memristor with various time difference (Δt) of preceding or lagging pulses set on it.
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