Abstract: The limitations of the von Neumann architecture have driven the demand for high-speed, nonvolatile, and energy-efficient memory solutions. Storage class memory (SCM) has emerged as a bridge between dynamic random access memory (DRAM) and NAND flash memory, offering high endurance and nonvolatility. Among SCM technologies, crossbar array features a cross-point structure to enhance the memory performance, relying on selector devices, such as ovonic threshold switching devices, to mitigate leakage currents and ensure reliable operation. Recently, selector-only-memory (SOM) has been explored as a novel approach in which memory operation is achieved using only selector devices, without additional memory cells. While previous studies have primarily focused on the switching mechanisms driven by polarity changes in the writing pulse, this paper presents a switching mechanism in SOM, where variations in the falling time of the writing pulse determine memory characteristics. The proposed method significantly improves the threshold voltage difference of SOM from 0.6 to 1.4 V and enhances endurance by four orders of magnitude compared with conventional methods. However, this also results in a degradation of 18 % in the off-current and larger cycle-to-cycle variations. To investigate the underlying mechanism, we employed the thermally assisted hopping and Poole-Frenkel models, revealing that the switching behavior is governed by the trap and carrier dynamics within the intermediate layer during the falling time of the writing pulse. This study provides new insights into SOM operations and contributes to the development of next-generation high-performance memory technologies.

Key words: Chalcogenide, Electronic trap, Unipolar operation, Pulse biasing scheme, Selector-only-memory