J. Mater. Sci. Technol. ›› 2015, Vol. 31 ›› Issue (6): 556-572.DOI: 10.1016/j.jmst.2014.12.005
• Orginal Article • Previous Articles Next Articles
Liubing Huang, Jia Grace Lu*
Received:
2014-11-24
Online:
2015-06-20
Published:
2015-07-23
Contact:
* Corresponding author.E-mail address: Supported by:
Liubing Huang, Jia Grace Lu. Synthesis, Characterizations and Applications of Cadmium Chalcogenide Nanowires: A Review[J]. J. Mater. Sci. Technol., 2015, 31(6): 556-572.
(a) A schematic diagram of a typical experiment setup for vapor phase growth. (b) A schematic diagram shows key processes in the VLS growth of nanowires. (c) Phase diagram of CdS-Sn shows the alloying, nucleation and growth processes[93].
(a) HRTEM image of single crystalline CdS nanowire grown along [0001] direction. Inset shows the corresponding SAED pattern[117]. (b) HRTEM image of CdS nanowire grown along 11?20 direction and the corresponding SAED (inset)[115]. (c) TEM and SAED of CdS nanowire grown along 21?1?1 direction[116]. (d) HRTEM image of CdS nanowire grown along 21?1?1[116].
Source-drain current Ids versus voltage Vds of a Sn doped CdS single nanowire field-effect transistor show good linearity under 0, 20, and 40 V gate voltages. Upper left inset: SEM image of a single wire FET. Lower right inset: source-drain current Ids versus gate voltage Vg plots under Vds = 2, 4, and 8 mV, respectively. (b) Temperature dependence of conductivity depicts the thermal activation of electrons from various donor levels [118].
(a) Photoluminescence spectra of CdS:Sn nanowire ensemble, taken at 4 K with an excitation density of 50 mW/cm2 at 325 nm. (b) The band structure for CdS:Sn determined from the PL peaks[118].
(a) SEM image of CdSe nanowires. (b) HRTEM image of CdSe nanowires grown along 101?0 direction. (c) HRTEM image of CdSe nanowires grown along [0001] direction[81].
(a) A typical IDS?VDS curve of undoped CdSe nanowires. Inset: SEM image of a typical CdSe nanowire FET. (b) IDS?VDS curves at different VG of In doped CdSe nanowires [127].
Photoluminescence (T = 10 K) and corresponding TEM images of CdSe nanowires with (a) and without (b) morphology defects. Scale bars: 200 nm. (c) Low temperature PL spectra of Au-catalyst CdSe nanowires (Au-NW) and seeded-grown CdSe nanowires (SG-NW)) [98].
(a) TEM image of a single CdTe nanowire grown along [111]. (b) HRTEM image of a CdTe nanowire and the SAED is shown in the inset[94]. (c) TEM and HRTEM image of a CdTe nanowire with a kink[87].
(a) Photoluminescence spectrum of CdTe nanowires measured at 5.0 K. (b) The band structure for CdTe illustrates the transition processes: donor bound excitons (DX), Y band, free electron to acceptor transitions (e, A), and donor-acceptor pair transitions (DAP) involving either shallow acceptors or deep level Au acceptors[94].
(a) Ids?Vds characteristics of an undoped CdTe nanowire at different gate voltages. Inset: the corresponding Ids?Vg curve. (b) Ids?Vds characteristics of a Sb doped CdTe nanowire at different gate voltages. Inset: the corresponding Ids?Vg curve [134].
(a) PL spectrum of the CdTe:Sb nanobelt ensemble, taken at 3.7 K with a excitation density of 90 mW/m2 at 633 nm. Several near band edge transitions are labeled: the free exciton FX, donor bound excitons (D,X), acceptor bound excitons (A,X) free electron to acceptor (e,A) transition, donor acceptor pair recombination (DAP) and their phonon replica. (b) Schematic band diagram depicts the impurity energy levels within the bandgap and recombination processes. One donor level and 3 acceptor levels are involved, and the binding energies are determined to be ED = 9 meV, EA1 = 61 meV, EA2 = 109 meV and EA3 = 130 meV [136].
(a) A schematic illustration of the back-gated CdS:Ga nanowire FET. (b) IDS?VDS curves at different VG. Inset: the corresponding IDS?VG curves measured at VDS = 1 V. (c) A SEM image of a top-gated CdS:Ga nanowire MISFET. (d) IDS?VDS curves measured at various VG. (e) A schematic illustration of the top-gated CdS:Ga nanowire FET. (f) IDS?VG curve measured at VDS = 1 V [119].
(a) A SEM image of a NOT logic circuit on one single CdS nanowire. (b) Transfer characteristics of the NOT gate presented in (a), with circuit diagram drawn in the inset. (c) Output voltage of a CdS nanowire NOR gate for the four input/output states: (0, 0), (0, 1), (1, 0), and (1, 1). (d) Output voltage of a CdS nanowire based NAND gate[142].
(a) A schematic diagram of the CdS/CdTe 3D nanopillar structure solar cell on PDMS substrate. (c) J?V characteristics of a flexible solar cell at different bending radii [13].
(a) Photoresponse of CdS:Cl nanowires. (b) Schematic diagram shows the measurement configuration for polarization-sensitive measurements. (c) Polarization sensitivity of CdS:Cl nanowire to the incident light with varied polarization angle[116].
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