Fig. 1. Schematic diagram of the device fabrication. (a) illustrates the device processing sequence and (b) a 3D cartoon of the modified UHV chamber. Firstly, S/D electrode regions are defined by lithography and exposed after developing, then the semi-finished device is placed into the UHV chamber, which consists of a planar ICP and a magnetron sputtering system. After plasma treatment and subsequent deposition of metal electrodes, the device is taken out of the chamber and completed by removing the sacrificial photoresist.

Fig. 2. (a) IDS-VBG transfer characteristics of mechanically exfoliated MoS2 FETs subjected to H2 plasma with different treatment times and input powers. 3-4 layer MoS2 flakes were chosen for fabricating these devices. (b) Corresponding statistical mobility values of the devices with treatment recipes shown in (a). IDS-VBG transfer characteristics of CVD-synthesized monolayer MoS2 based FETs (c) without and (d) with H2 plasma treatment (100 W, 30 min). Drain-source bias is 1 V for all devices.

Fig. 3. (a) Top view of crystal structures of pristine and modified 1 L MoS2 nanosheet with top S atoms at both ends are etched by plasma. (b) The three-dimensional diagram of MoS2 FET with plasma treatment. (c) Charge densities of the valence band maximum and conduction band minimum of the MoS-MoS2-MoS nanosheet. The iso-value is 0.003 e ?-3. (d) Electronic band structure of pristine and modified monolayer MoS2 nanosheet. The Fermi energy Ef is set at 0 eV in the dashed line.