J. Mater. Sci. Technol. ›› 2024, Vol. 201: 149-156.DOI: 10.1016/j.jmst.2024.01.098

• Research Article • Previous Articles     Next Articles

Quantum transport in WSe2/SnSe2 tunneling field effect transistors with high-k gate dielectrics

Hailing Guoa, Zhaofu Zhangb, c,*, Chen Shaoa, Wei Yua, Qingzhong Guia, Peng Liud, Hongxia Zhonge, Ruyue Caof, John Robertsona,f, Yuzheng Guoa,*   

  1. aSchool of Electrical Engineering and Automation, Wuhan University, Wuhan 430072, China;
    bThe Institute of Technological Sciences, Wuhan University, Wuhan 430072, China;
    cHubei Key Laboratory of Electronic Manufacturing and Packaging Integration, Wuhan University, Wuhan 430072, China;
    dGuangxi Power Grid Company Co., Ltd., Nanning 530023, China;
    eSchool of Mathematics and Physics, China University of Geosciences, Wuhan 430074, China;
    fDepartment of Engineering, University of Cambridge, Cambridge CB2 1PZ, United Kingdom
  • Received:2023-11-15 Revised:2023-12-18 Accepted:2024-01-07 Published:2024-12-01 Online:2024-04-06
  • Contact: * E-mail addresses: zhaofuzhang@whu.edu.cn (Z. Zhang), yguo@whu.edu.cn (Y. Guo) .

Abstract: Combining two-dimensional materials and high-k gate dielectrics offers a promising way to enhance the device performance of tunneling field-effect transistor (TFET). In this work, the device performance of WSe2/SnSe2 TFET with various gate dielectric materials is investigated based on quantum transport simulation. Results show that TFETs with high-k gate dielectric materials exhibit improved on-off ratio and enhanced transconductance. The optimized WSe2/SnSe2 TFET with TiO2 gate dielectrics achieves an on-state current of 1560 μA/μm and a subthreshold swing (SS) of 48 mV/dec. The utilization of high-k gate dielectric materials results in shorter tunneling length, higher transmission efficiency, and increased electron tunneling probability. The performance of the WSe2/SnSe2 TFET would be affected by the presence of the underlap region. Moreover, WSe2/SnSe2 TFETs with La2O3 dielectric can be scaled down to 3 nm while meeting high-performance (HP) device requirements according to the International Technology Roadmap for Semiconductors (ITRS). This research presents a practical solution for designing advanced logic devices in the sub-5 nm technology node.

Key words: Tunneling field-effect transistor, High-k gate dielectrics, Quantum transport calculation