J. Mater. Sci. Technol. ›› 2021, Vol. 60: 21-26.DOI: 10.1016/j.jmst.2020.04.059
• Research Article • Previous Articles Next Articles
Tian-Yu Wang, Jia-Lin Meng, Qing-Xuan Li, Lin Chen*(), Hao Zhu, Qing-Qing Sun*(
), Shi-Jin Ding, David Wei Zhang
Received:
2020-03-18
Revised:
2020-04-21
Accepted:
2020-04-23
Published:
2021-01-10
Online:
2021-01-22
Contact:
Lin Chen,Qing-Qing Sun
Tian-Yu Wang, Jia-Lin Meng, Qing-Xuan Li, Lin Chen, Hao Zhu, Qing-Qing Sun, Shi-Jin Ding, David Wei Zhang. Forming-free flexible memristor with multilevel storage for neuromorphic computing by full PVD technique[J]. J. Mater. Sci. Technol., 2021, 60: 21-26.
Fig. 1. (a) Schematic diagram of the flexible RRAM with structure of PET/ITO/NiO/Ag fabricated by PVD. (b) AFM height image of NiO film on the flexbile substrate. (c) High-resolution XPS spectra of Ni 2p region and (d) O 1s region. (e) The cross-section TEM image of the flexible device, indicating the thickness of ITO/NiO/Ag are 50 nm, 30 nm and 70 nm, respectively. (f) Energy dispersive X-ray (EDX) mapping results of Ag, Ni and Sn elements distribution in the device.
Fig. 2. (a) Schematic illustration of the NiO-based RRAM measuring electrical characteristics under flat state. (b) Forming-free behavior demonstrated by reset operation with no need of pre-programing large positive voltage. (c) Typical bipolar resistive switching characteristic of NiO-based RRAM with Icc of 1 mA. (d) Conduction mechanism of device under positive voltage. (e) The statistical distribution of set and reset voltages obtained from 100 switching cycles. (f) DC switching endurance of NiO-based RRAM.
Fig. 3. (a) I-V curves of device under different compliance currents, including 150 μA, 300 μA, 500 μA and 1 mA. (b) The four low resistance states of device under different compliance currents, including State 1, State 2, State 3 and State 4. (c) High resistance states of device under different compliance currents are controlled at the same level, representing the State 5. (d) Retention characteristics of 5 resistance states for over 10 ks. (e) Reversible resistive switching of 20 cycles with different compliance currents. The read voltage is 0.1 V.
Fig. 4. (a) Schematic illustration of biological synapse, where the pre-spike could induce post-synaptic current. (b) Excitatory post-synaptic current induced by a single voltage pulse (1 V, 10 ms) in electronic synapse of ITO/NiO/Ag. (c) Forgetting curve of electronic synapse after applying a pre-spike on the top electrode, which is monitored for over 60 s with a small bias of 0.1 V. (d) Paired-pulse facilitation behavior simulated by NiO-based artificial synapse by applying a paired of pulses (1 V, 50 ms) with interval time of 1 s. (e) PPF index versus interval times between a paired of pulses. (f) Long-term potentiation/depression characteristics simulated by applying consecutive positive and negative pulses. There are 100 modulated resistance states in this process.
Fig. 5. (a, b) Illustration of flexible NiO-based device under (a) tensile and (b) compressive stress. (c, d) The resistive switching characteristics of flexible device under (c) tensile and (d) compressive states (radius = 10 mm).
Device Architectures | Forming-free RRAM | Type of Fabrication Process | Set/Reset Voltage (V) | Set/Reset Power (W) | Multi-level Storage | Synaptic plasticity | Refs. |
---|---|---|---|---|---|---|---|
graphene/MoS2-xOx/graphene | No | 6 | 1/-1 | 10-5/10-4 | No | No | [ |
Al/PI:PCBM/Au | N/R | 5 | 3/4 | 10-5/10-2 | No | No | [ |
Au/α-MoO3/Cr/Au | No | 4 | 3/5 | 10-6/10-2 | Yes (3 levels) | No | [ |
TiN/TiON/HfO2/Pt | No | 4 | -1/1 | 10-5/10-3 | No | Yes | [ |
Au/h-BN/Ti/Au | No | 3 | 2/-1.5 | 10-12/10-3 | No | Yes | [ |
Al/PS:PCBM/Au/Pt | N/R | 3 | 3/4 | 10-7/10-5 | No | No | [ |
ITO/PbS QDs@PMMA/Ag | N/R | 2 | 1.1/-1.1 | 10-3/10-1 | Yes (4 levels) | No | [ |
Pt/GO/Ti/Pt | Yes | 2 | 3.5/-3.5 | 10-7/10-4 | Yes (4 levels) | No | [ |
ITO/NiO/Ag | Yes | 1 | 0.79/-1.23 | 10-5/10-4 | Yes (5 levels) | Yes | This work |
Table 1 Comparison of this work with state-of-the-art memristors.
Device Architectures | Forming-free RRAM | Type of Fabrication Process | Set/Reset Voltage (V) | Set/Reset Power (W) | Multi-level Storage | Synaptic plasticity | Refs. |
---|---|---|---|---|---|---|---|
graphene/MoS2-xOx/graphene | No | 6 | 1/-1 | 10-5/10-4 | No | No | [ |
Al/PI:PCBM/Au | N/R | 5 | 3/4 | 10-5/10-2 | No | No | [ |
Au/α-MoO3/Cr/Au | No | 4 | 3/5 | 10-6/10-2 | Yes (3 levels) | No | [ |
TiN/TiON/HfO2/Pt | No | 4 | -1/1 | 10-5/10-3 | No | Yes | [ |
Au/h-BN/Ti/Au | No | 3 | 2/-1.5 | 10-12/10-3 | No | Yes | [ |
Al/PS:PCBM/Au/Pt | N/R | 3 | 3/4 | 10-7/10-5 | No | No | [ |
ITO/PbS QDs@PMMA/Ag | N/R | 2 | 1.1/-1.1 | 10-3/10-1 | Yes (4 levels) | No | [ |
Pt/GO/Ti/Pt | Yes | 2 | 3.5/-3.5 | 10-7/10-4 | Yes (4 levels) | No | [ |
ITO/NiO/Ag | Yes | 1 | 0.79/-1.23 | 10-5/10-4 | Yes (5 levels) | Yes | This work |
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