Physical Mechanism and Performance Factors of Metal Oxide Based Resistive Switching Memory: A Review
Cong Ye1, Jiaji Wu1, Gang He2, Jieqiong Zhang3, Tengfei Deng1, Pin He1, Hao Wang1
1 Hubei Collaborative Innovation Center for Advanced Organic Chemical Materials, Hubei Key Laboratory of Ferroelectric and Dielectric Materials and Devices, Faculty of Physics and Electronic Science, Hubei University, Wuhan 430062, China
2 School of Physics and Materials Science, Radiation Detection Materials & Device Lab, Anhui University, Hefei 230039, China
3 Department of Electrical Engineering, City University of Hong Kong, Hong Kong Special Administrative Region, China
* Corresponding author. Ph.D.; Tel.: +86 551 63861793. E-mail address:ganghe01@issp.ac.cn (G. He). ** Corresponding author. Ph.D.; Tel.: +86 27 88665004. E-mail address:nanoguy@126.com (H. Wang).
Abstract

This review summarizes the mechanism and performance of metal oxide based resistive switching memory. The origin of resistive switching (RS) behavior can be roughly classified into the conducting filament type and the interface type. Here, we adopt the filament type to study the metal oxide based resistive switching memory, which considers the migration of metallic cations and oxygen vacancies, as well as discuss two main mechanisms including the electrochemical metallization effect (ECM) and valence change memory effect (VCM). At the light of the influence of the electrode materials and switching layers on the RS characteristics, an overview has also been given on the performance parameters including the uniformity, endurance, the retention, and the multi-layer storage. Especially, we mentioned ITO (indium tin oxide) electrode and discussed the novel RS characteristics related with ITO. Finally, the challenges resistive random access memory (RRAM) device is facing, as well as the future development trend, are expressed.

Keyword: RRAM (resistive random access memory); Transition metal oxide; Conductive filament; Resistive switching
1. Introduction

The resistive switching (RS) phenomenon was firstly reported in a series of binary oxides by Hickmott in 1962[1]. Until now, the scientific and industrial interests on the resistance random access memory (RRAM) have already lasted for more than 50 years. Extensive research on the physical analyses and mechanisms has been performed to understand the electrical phenomena in the 1960s and 1970s[2, 3, 4, 5, 6]. In fact, there are various candidates (e.g. magnetic random access memory [MRAM], ferroelectric random access memory [FRAM], phase change random access memory (PRAM) and resistive random access memory [RRAM][10, 11, 12, 13, 14, 15, 16]) for next-generation memory to replace current flash memory for its disadvantages of high operating voltage, low operating speed, high power consumption and the scaling limitation to 16 nm[7, 8, 9]. Fortunately, RRAM has been considered to be the most promising one, owing to its advantages of simple structure, low operating power and fast switching speed[17, 18]. The RRAM structure is a switching layer sandwiched between two metal electrodes, which is a metal-insulator-metal (MIM) structure. It has been found that a great variety of materials including transition metal oxides, perovskite, organic materials have shown RS characteristics[19, 20, 21, 22]. Owing to the extreme diversity of RS materials, it is not possible to review all the related issues. Among them, metal oxide based resistive switching memory is widely investigated due to its simple composition, low cost, and compatibility with CMOS (complementary metal-oxide-semiconductor transistor) technology, such as NiO[23, 24, 25, 26], TiO2[27, 28, 29, 30, 31], ZrO2[32, 33], Al2O3[34, 35], HfO2[36, 37, 38, 39, 40, 41], ZnO[42, 43, 44], and WO3[45]. It has been reported that memory cells such as TiN/TiOx/HfOx/TiN have shown switching speed of ~5 ns [46]. Lee et al.[47] demonstrated a TaOx-based asymmetric passive switching device with extreme cycling endurance of over 1012. Furthermore, the structure of TiN/HfOx/Pt exhibited data retention properties of 104 s at 85 ° C[48]. In summary, research has indicated that excellent performance of ultrahigh switching speed, good switching endurance and reliable data retention has been achieved in metal oxide based resistive switching memory.

In this review, we focused on the metal oxide based RRAM. Although we limit to the metal oxide in this review, there are still some meaningful work needed to be summarized. Recent research on RRAMs still faces challenges such as wide resistance distribution and non-uniformity of SET/RESET voltage. Also, the physical mechanism in the SET/RESET process for RRAM is still unclear. Therefore, at first, the basic working principles of the device and the switching mechanism will be highlighted in Sections 2 and 3. Secondly, the effect of electrode materials and the structure of switching layers on the performance parameters including uniformity and power consumption will be critically discussed in Sections 4 and 5. Finally, an outlook for RRAM application and its challenges current being faced such as high power consumption, operating stability and controversial RS switching mechanisms will be presented.

2. RS Behavior of the Metal Oxide Based Resistive Switching Memory: Unipolar and Bipolar

The RS characteristics of metal oxide RRAM can be classified into two switching modes: unipolar and bipolar. Unipolar RS behavior refers to the switching direction depending on the amplitude of the applied voltage rather than the polarity, as illustrated in Fig. 1(a). Bipolar RS behavior refers to the switching direction dependent on the polarity of the applied voltage, and thus the set process can only occur at one polarity and the reset process can only occur at reverse polarity, as shown in Fig. 1(b). The compliance current is an important parameter to be considered in the set process for both unipolar and bipolar RRAM. It is recommended to enforce a set compliance current to avoid a permanent breakdown of the device[49]. In addition, changing the value of compliance current and stop voltage can realize multilevel storage for the RRAM. Section 5 will describe it in detail[46].

Fig. 1. Typical I-V curves of unipolar (a) and bipolar (b) switching modes and the current compliance (CC) is adopted to avoid permanent dielectric breakdown of devices [49].

As for a unipolar RRAM, the device usually has a symmetric structure, which means that the same material has been used as the top electrode (TE) and the bottom electrode (BE), such as Pt/NiO/Pt[50], Pt/TiO2/Pt[51], Pt/ZnO/Pt[52], Pt/ZrO2/Pt[53], Pt/HfO2/Pt[54]. In contrast, the device structure of bipolar switching is usually asymmetric, which means that different materials are used as TE and BE, such as Pt/NiO/SrRuO3[55], Pt/TiO2/TiN[56], TiN/ZnO/Pt[52], Ti/ZrO2/Pt[57], and TiN/HfO2/Pt[48]. For different switching modes, the reset mechanism is a controversial issue. Based on the conducting filament (CF) theory, it can be classified into two main CF disruption mechanisms: thermal dissolution model[26]and ionic migration model[58]. The former is often explored to explain the unipolar RS characteristics, whereas the latter can be normally applied to explain the bipolar RS characteristics. It is reported that the reset mechanism is greatly dependent on the electrode/oxide interfaces[38]. For unipolar RRAM, noble metals such as Pt or Ru are often applied as both top and bottom electrodes. On the other hand, the bipolar RRAM active materials such as TiN or Ti are normally used as electrodes, and the interfacial layer is easy to be formed in the operating process. Yu and Wong[59] proposed a universal reset mechanism for both unipolar/bipolar modes. Firstly, for the unipolar device, the mainstream viewpoint of reset mechanism is due to a thermal dissolution of CFs by local Joule heating[60, 61, 62]. Oxygen ions (O2-) would be accumulated near the anode with a concentration gradient during the set process. Subsequently, the Joule heating would activate O2- to combine with the oxygen vacancies (V02+) during the reset process to make the CF disconnect. This thermal dissolution model results in the unipolar reset process. However, Yu et al.[63] put forward a question about this: if the CF is considered to be “ dissolved” by local Joule heating, the CF may rupture in the middle of the filament where the temperature is the highest[64] rather than occur at the region near the anode.

As concerned as the bipolar device, the interfacial layer may act as an oxygen diffusion barrier, and thus the thermal diffusion mentioned above is not sufficient to result in the reset process. Only by the application of a reversed electric field can the oxygen ions drift back to cause the CFs to rupture. This is a so called ionic migration model. As the interfacial oxide layer was observed, Yu et al.[63] maintained that it may act as an “ oxygen reservoir” , which stores the oxygen ions during the set process and then drives them back during the reset process. Besides, the “ oxygen reservoir” can prevent the oxygen from escaping from the device to ambient. Therefore, this concept of an “ oxygen reservoir” is envisioned, which can explain some switching characteristics for bipolar RRAMs. For example, in Fig. 2(a), the formed interface of ZrON can serve as an oxygen reservoir to hamper the oxygen ions' diffusion further away from the RS layer HfOx and provide sufficient oxygen ions in the reset process, which is attributable to the robust cyclic endurance property of Pt/HfOx/ZrNx memory cell, as demonstrated in Fig. 2(b)[65].

Fig. 2. (a) The cross-section TEM image of Pt/HfOx/ZrNx stacks. (b) Endurance characteristics of the Pt/HfOx/ZrNx structure in the electric pulse switching mode [65].

3. Physical Mechanism of Metal Oxide Based Resistive Switching Memory

The origin of RS behavior can be roughly classified into the conducting filament type and the interface type[66]. Here, we adopt the filament type to study the metal oxide based resistive switching memory, which considers the migration of metallic cations and oxygen vacancies. Accordingly, we discuss two main mechanisms: the electrochemical metallization effect (ECM) and the valence change memory effect (VCM).

In general, ECM can be adopted to explain RRAM which consists of an electrode made from an electrochemically active metal, such as Ag[19], Cu[67], or Ni[68], and an electrochemically inert metal counter electrode such as Pt[69], Au[70], or Ir[71]. Yang et al.[19] studied Ag/ZnO:Mn/Pt memory cell and successfully observed nanoscale Ag conductive bridge penetrating through the storage thin film by scanning transmission electron microscopy (STEM) with high-resolution energy dispersive X-ray spectroscopy (EDX), which could account for the high conductivity in the ON-state device, as shown inFig. 3. Fig. 4 illustrates a schematic diagram for the switching mechanism of Ag/ZnO:Mn/Pt devices. When a positive voltage is applied to Ag TE, oxidation process of Ag atoms occurs and Ag+ cations are generated, which could be described in Fig. 4(a). The Ag+cations drift to Pt BE under the electrical field and are reduced by electrons flowing from the cathode as shown in Fig. 4(b). The successive precipitations of metal atoms at the cathode lead to a growth of the Ag protrusion, which finally reaches the TE and forms a conductive path in the ON state as shown in Fig. 4(c). When the polarity of the applied voltage is opposite, an electrochemical dissolution takes place somewhere along the bridge, and switches to the OFF state (Fig. 4(d)). In Fig. 3, the conductive bridge composed of Ag can be detected at ~8 nm underneath the bridge/Pt interface. This result shows that the conductive bridge has not only connected the electrode pair completely but also extended into Pt BE. Based on the above examples, we believe that more studies about manipulation or observation on the CF need to be carried out to further prove ECM mechanism. Based on the above examples, we believe that the ECM mechanism does not always prevail whenever electrochemically active metals such as Cu or Ag are utilized in a resistive switching cell. In the reported Cu/Cu-TCNQ/Al (TCNQ denotes 7, 7′ , 8, 8′ -tetracyanoquinodimethane) memory cell thirty years ago, a charge transfer reaction between Cu and TCNQ was claimed to be responsible for the resistive switching effect; subsequently, a variety of control experiments indicated that the resistive switching was due to the Al oxide/Al hydroxide layers acting as the electrode[72, 73]. In consequence, as for ECM effect, when Cu or Ag is selected as the electrode for RRAM, the certain mechanism needs to be verified by specific experiment.

Fig. 3. Z-contrast image and high-resolution EDX analysis in STEM mode for the bridge-like region in ON-state device. A line profile concerning the intensity of Ag along the bridge [19].

Fig. 4. A schematic diagram for mechanism of resistive switching effect in ECM cell: (a) Ag oxidize to ions at the Ag electrode(Ag → Ag+ + e-); (b) Ag+ migrate to Pt electrode and is reduced therein(Ag+ + e-→ Ag); (c) precipitations of Ag at the Pt electrode and finally form a highly conductive filament in the cell, setting the system into LRS; (d) an electrochemical dissolution of the filament takes place, resetting the system into HRS[19].

As concerned as the valence change memory effect (VCM) RRAM, it has much difference with RRAM. It is not necessary to consist of an active electrode and an inert electrode. Here, we take the structure of Pt/STO/Nb-STO as an example to illustrate the VCM memory. The ions' migration micro-process is as follows: When the positive bias is applied on the Pt electrode, a large amount of Vo2+ would accumulate on the Nb-STO electrode, and these Vo2+ would form the similar trapezoid shape of “ actual cathode” as shown inFig. 5(a)[74]. The area of “ virtual cathode” would increase by the improvement of positive bias, and Vo2+ would reach the anode finally. At the same time, oxygen ions near the anode lose electron and produce O2 bubble. The VCM cells switch from high resistance state (HRS) to low resistance state (LRS).

Fig. 5. (a) Trapezoid shape of “ virtual cathode” was formed under the positive bias. (b) Typical I-V curves of Pt/STO/Nb-STO device [74].

When negative bias is applied, the O2- migrates to cathode and combines with the oxygen vacancies. This conductive path will be disconnected, the cell switched from LRS to HRS. The typical I-V curves of Pt/STO/Nb-STO memory device are as shown in Fig. 5(b). Especially, more studies about manipulation or observation on the CF need to be carried out to further prove VCM mechanism.

4. Effect of Electrode Materials on the Metal Oxide Based Resistive Switching Memory

Electrode materials play an important role in the RS property[52, 75, 76]. In general, when the electrode is selected for the RRAM device, the following key factors of the electrode material should be mainly considered: the activity of the electrode, work function, and the interface between the electrode and the switching layer for the RRAM device[77]. Seo et al.[78] found that the RS behavior for NiO films based RRAM is dependent on the interface barrier height between the electrode and the switching layer. When Pt or Au is used as the top electrode, Ohmic contact is formed and the voltage drop between electrode and switching layer can be ignored, and thus a relatively low voltage can induce the resistive switching[79]. When Ti is used as the top electrode and Schottky contact is formed, the voltage drop should be considered and a higher voltage is needed to induce the resistive switching. Meanwhile, Yang and Rhee[80] also reported the similar results by investigating the structure of Pt/Cu2O/bottom electrode. In Table 1, some commonly used electrode materials were summarized for metal oxide based resistive switching memory.

Table 1 Summarized electrode materials on the metal oxide based resistive switching memory
4.1. Active electrodes

In most cases, the unipolar RS behavior is obtained with a noble metal electrode, such as Pt or Ru. If one of the electrodes is replaced by active electrode such as Ti or TiN, the bipolar RS behavior is obtained. It is reported that the RS uniformity of the RRAM device can be improved by utilizing Ti as the electrode[52]. In comparison with Pt/ZrO2/Pt and Al/ZrO2/Pt, Lin et al.[52] found that the structure of Ti/ZrO2/Pt device showed a narrower distribution of switching parameters, such as Ron and Roff, Von and Voff as shown in Fig. 6. Meanwhile, metal electrodes, such as TiN, TaN and ZrNx, also show excellent performance for RS memory. For example, the structure of ZrNx/HfOx/Pt exhibits better endurance (> 106) and longer retention time (104 s) by comparing with the Pt/HfOx/Pt [65]. This is possibly attributed to the formation of ZrON interface, which is served as an “ oxygen reservoir” , and thus improves the performance and reliability of the device [92-95].

Fig. 6. Variations of the resistance and voltage parameters on ZrOx RRAM (Ron and Roff measured at 0.3 V)[52].

Besides, we discuss another important active electrode: ITO electrode. This transparent electrode has already been utilized in many electronic devices, as well as memory units because of its excellent conduction, light transmittance, and high hardness[96, 97]. Moreover, it is a highly degenerate n-type semiconductor and its good conductivity originates from the carriers including oxygen vacancies and the activated Sn4+ ions on In3+ sites. We have reported the TiN/HfOx/ITO memory cells, which shows self-compliance current phenomenon as shown in Fig. 7(a). The reason why ITO electrode has a small Vsetis clarified by discussing a possible resistive mechanism as illustrated in Fig. 7(b).

Fig. 7. Switching characteristic curves of TiN/HfO2/ITO device for 10 switching cycles with increasing voltage are shown, LRS current increases slightly and shows self-compliance to 800 µ A (ICOMP). (b) In SET process, schematic diagram of driving mechanism for TiN/HfO2/ITO memory cell is given. The redox reactions to form the conducting filament are shown together[48].

According to the CF theory, the filament is made of oxygen vacancies or metallic ions. If the ITO electrode is applied in RRAM, the existence of many Sn4+ ions may affect the drift of O2- in the HfO2 layer because Sn4+ ions are active and flexible to move in the ITO film. This would result in the difference in CF formation/rupture, which in turn induces the different switching behavior. We have done much work on ITO electrode and found that ITO electrode can relate to the redox process in the MIM cell, which have advantages on the improvement of RS performance, such as reducing the power consumption of the device, providing robust endurance and so on[42].

4.2. Electrodes with buffer layer

An electrode with a buffer layer is usually adopted to improve the RS characteristics of the RRAM device. Fig. 8(a) illustrates a schematic diagram of 1T1R unit (1 Transistor and 1 RRAM). The transistor is cascaded with a stacked TiN/Ti/HfO2/TiN RRAM cell to provide compliance current. Fig. 8(b) shows the HR-TEM image of TiN/Ti/HfOx/TiN stacked layers[98]. Lee et al.[46] reported that this kind of 1T1R structure exhibited excellent RS performance, including high-speed operation (< 10 ns), large ON/OFF ratio (> 100), long high-temperature lifetime, multilevel storage, high device yield (~100%), and the TiN/Ti/HfO2/TiN memory cells have been successfully integrated in a 0.18 µ m COMS process. Considering the TiN/Ti electrode, the buffer layer Ti film served as a capping layer, which can deplete the oxygen atoms from the HfOx thin film and act as an oxygen reservoir. Also, this group also used AlCu and Ta as the capping layer for the HfOxmemory cell, and the device exhibited stable bipolar switching behavior but had a small ON/OFF ratio (~4) [89]. The oxygen capture ability of capping metal layer may be responsible for these results[98].

Fig. 8. (a) A typical 1T1R structure of RRAM with HfOx; (b) HR-TEM image of the TiN/Ti/HfO2/TiN stack with 20 nm thick HfO2 layer[98].

In addition, Govoreanu et al.[99] reported the TiN/Hf/HfOx/TiN RRAM stack with the size of 10 nm × 10 nm, which has become the smallest HfO2-based RRAM cell in the research field so far. It can be seen that TiN electrode is also designed with Hf thin film as the buffer layer. We can conclude that different capping layers lead to the variation of RS behavior, and hence selecting the material as the buffer layer is crucial.

4.3. Electrode using novel materials

Despite the commonly used electrodes as mentioned above, researchers intend to find the applications of novel materials to the RRAM devices, such as carbon nanotube, n+-Si, and graphene. Chai et al.[85] have reported switching characteristics of an amorphous carbon (a-C) layer with carbon nano-tube (CNT) electrodes for ultra-dense memory. The device was proposed for solving the sneak leakage current in cross-point memory, which successfully further increased the density of the memory.

Moreover, n+-Si electrode, which is normally used in the transistor, also can be used in RRAM device. Fig. 9 shows the typical I-V curves of n+-Si/ZrO2/Pt memory cell before and after programming progress, which demonstrated that resistance ratio (ON/OFF) exceeds 106 with a 1 V readout voltage. Especially, a pronounced self-rectifying effect, with the rectification ratio as high as 104, is observed after programming process. The emergence of self-rectifying effect might be that the current conduction is suppressed by the Schottky barrier, which exists in the interface between n+-Si electrode and SiOx/ZrOx layers [86].

Fig. 9. The typical I-V curves of n+-Si/ZrO2/Pt structure, a pronounced self-rectifying effect is obtained after programming[86].

At the same moment, many devices, such as n+-Si/HfOx/Ni [100], Ni/AlOy/n+-Si[101], and n+-Si/ZrO2/Pt[86], have shown the self-rectifying effect as a result of using n+-Si electrode. As we already know, self-rectifying property can largely alleviate the crosstalk in crossbar array without extra rectifying diodes, which correspond to the 1D1R (one diode-one resistance). Therefore, the memory with self-rectifying properties has potential applications in high-density crossbar memory.

5. Effect of Doping and Structure Design on the Switching Layer

It was reported in 2008 that the CMOS process node would be scaled to 22 nm in 2014, which was near to the limit[102]. To meet the urgent need of an increase in storage density for RRAM development, it is very challengeable for RRAM to achieve further scaling down. Therefore, it is difficult to achieve an obvious increase of storage density only through the simple scaling down of the device size. However, multilevel storage can significantly enhance the storage density without much change in current technologies. Multilevel storage refers to the ability of a memory cell to exhibit reproducible resistive switching between multiple resistance states and store multiple values consequently[102]. Lee et al.[46] proposed that multilevel storage can be achieved by controlling either compliance current (Icomp) or operating voltage. In this chapter, we mainly considered the doping effect on the metal oxide switching layer, as well as the structure design of the switching layer.

5.1. Doping in the switching layer for the metal oxide based resistive switching memory

To clarify the influence of doping on the switching layer, Lee et al.[103] investigated various doped metal oxides and found that doping in the switching layer for RRAM can realize favorable memory characteristics such as reliability under programming cycles, good data retention, potential multi-bit operation, highly scalable property, and fast switching speed.

Low-power and high speed resistive switching of Pt/Ti:NiO/Pt memory cell has been reported[104]. Because of doping the Ti into the NiO memory, this memory achieved a faster reset time (< 5 ns) than that of the pure NiO film, as shown in Fig. 10(a). In addition, the abnormal set phenomena in the pure NiO film as illustrated in Fig. 10(b), can also be suppressed, for the reason that an oxygen reservoir was introduced and Ti-O bonds were formed due to the Ti doping.

Fig. 10. Comparison of the reset speed between NiO and Ti:NiO at: (a) Vcell = 1.0 V, (b) Vcell = 1.6 V, abnormal set phenomena occur during the reset process[104].

On the other hand, some doping effect can be presented as forming-free for the memory cell. For TiN/Ge:HfO2/Pt memory cell[105], the Ge atoms diffused into the HfO2 layer and the oxygen vacancies increased, and thereby the memory is forming-free. Moreover, the uniformity of this cell is greatly enhanced by Ge doping, due to the low oxygen-vacancy formation energy. In particular, the self-compliance current phenomenon is achieved. Wang et al.[106] reported that Pt/Cu:HfO2/Pt memory demonstrated good electrical characteristics: DC endurance over 100 cycles, a long retention over 105 s, a fast operation speed and large storage windows about 107 in 9 µ m2 devices. Among these performance parameters, the endurance refers to the number of set/reset cycles[107]. In general, typical flash shows a maximum number of write cycles between 103 and 107, and accordingly, RRAM should provide at least the same endurance, and even a better one[108]. Retention refers to the data retention time, the length of time of a memory cell should stay in one state after programming or erasing[109]. For RRAM device, the data generally need to be stored more than ten years. During this process, it needs to consider the influence of the temperature and continuous voltage signal of read operation. In short, doping in the switching layer is an effective way to improve the performance of RRAM.

5.2. Switching layer with bi-layer for the metal oxide based resistive switching memory

To make a further study on the potential applications of high k based RRAMs, the structure of switching layer is needed to design for the excellent performance and reliability of RRAM device, including the low power consumption and good uniformity [110-112]. Double-layer structure RRAM is proven to be a feasible and effective way[97]. For example, Ni/GeOx/HfON/TaN RRAM has been reported with a very low set current of 0.1 µ A and reset current of -0.3 nA, GeOx was served as the switching layer while HfON was used as the charge-trapping layer, which contributed to the ultra-low switching power of the device [84].

As for the bi-layer structure, the role of each layer is different. One layer with lower resistivity can act as series resistance, and the other one has higher resistivity[113]. Normally, the RS behavior does not occur in the whole layer but occurs in the higher resistivity switching layer, and the lower resistivity layer can improve the resistance of ON state. The higher resistance value of ON state would bring out lower reset current (Ireset) and power consumption.

Many bi-layer devices can obtain the low power consumption. A typical example of Barrier/TMO1/TMO2/Barrier structure device is shown in Fig. 11, which exhibits the set power consumption ~3 µ W and power consumption ~80 nW. Compared with the previous TMO2/TMO1 structure without the barrier, the set current of Barrier/TMO1/TMO2/Barrier structure reduces from 50 µ A to 1 µ A, and the reset current reduces to 30 nA as shown in Fig. 12<sup>[114].

Fig. 11. (a) Structure of Barrier/TMO1/TMO2/barrier; (b) the structure of TMO1/TMO2[114].

Fig. 12. Typical I-V characteristic of Barrier/TMO1/TMO2/barrier. (b) Typical I-V characteristic of TMO1/TMO2without barrier layer[114].

In Table 2, some low power RRAM devices are summarized. By the comparison of the Iresetand power consumption between the bi-layer and the single layer, we conclude that the reduction in power consumption might be due to the application of the bi-layer.

Table 2 Low power RRAM devices are summarized

Apart from low-power consumption mentioned above, good uniformity can also be obtained by the application of bi-layer structure. Uniformity is the variation of the resistance switching including temporal fluctuations (cycle to cycle) and spatial fluctuations (device to device). It mainly consists of device parameters such as set voltage, reset voltage, and HRS and LRS resistance distribution, which are essential to large-scale manufacture of RRAM[38]. To understand the relationship between bi-layer structure and uniformity, the characteristics of TiN/HfOx/Pt and TiN/AlOx-HfO2/Pt[117] memory cells have been investigated. By embedding a thin AlOx buffer layer (~5 nm) between the HfOxand the TiN top electrodes, the TiN/AlOx-HfOx/Pt cell exhibited much better characteristics. In particular, HfOx/AlOx bi-layer RRAM devices show a better switching uniformity of the switching voltages and resistances distribution than the single layer HfOxdevices, as shown in Fig. 13. The improvements of the uniformity in the HfOx/AlOx bi-layer device might be because the diffusion of Al atoms into HfOx could stabilize the CFs to reduce the randomness of RS [118]. Another explanation is that the reset process usually can only rupture the upper part of the CFs, and the so-called “ virtual cathode” in the bottom AlOx layer tends to serve as the seeds to re-grow the CFs. However, further work is still needed to clarify the reason for the improvement of uniformity.

Fig. 13. (a) Distribution of set/reset voltages from 200 DC sweep cycles are obtained, bi-layer sample has better uniformity. (b) Distribution of HRS/LRS resistance obtained, bi-layer sample exhibit the better uniformity[117].

5.3. Switching layer with multi-layer for the metal oxide based resistive switching memory

In addition to the bi-layer structure, the application of multi-layer structured memory cell also exhibits excellent performance. Fang et al.[119] present the four layer structure of TiN/HfOx-TiOx-HfOx-TiOx/Pt memory cell; compared with HfOx-based single-layer device, a multi-layer device achieves the forming-free behavior. Moreover, the uniformity of parameters, such as set and reset voltage, HRS and LRS resistance distributions are significantly improved. It is possible that Ti doping effect and the confinement of conduction filament within different dielectrics layers contribute to the improvement of uniformity. Based on this structure, Yu et al. [120] have engineered oxide-based synaptic devices by stacking multiple layers of Pt/HfOx/TiOx/HfOx/TiOx/TiN (from bottom to top). Stacked multi-layer can be applied to the potential and attractive application of neuromorphic computing, which could emulate the brain and realize visual image processing and understanding or auditory speech recognition [121]. Their group gradually modulated hundreds of resistance states by applying hundreds of identical pulses, and this referred resistance modulation methodology has an obvious advantage over the previous widely used methodology of varying pulse amplitude or width [122, 123], which will greatly simplify the neuron circuit design and optimize the oxide-based resistive switching electronic synaptic device. Furthermore, the multi-level resistance states based on this structure were achieved by varying the sweep stop voltages shown in Fig. 14. It can be seen that the set process is abrupt while the reset process is gradual. We may ask whether the gradual reset process is necessary for the achievement of the multi-level storage. Moreover, another issue should be considered, whether resistance modulation in this oxide-based synaptic device is resulted from the interface defects between each layer (HfOx/TiOx). To highlight the possibility of high-density application of RRAM, Lee et al.[124] investigated the Pt/Ta2O5-x/TiOxNy/TiN/Ta2O5-x/Pt matrix and found two bipolar resistive switching elements on the structure of Pt/Ta2O5-x/TiOxNy and TiN/Ta2O5-x/Pt as illustrated in Fig. 15. The four layer structure exhibited multi-level storage function and at each crossbar point with three distinguishable resistance states (HRS, LRS and IRS). In summary, the application of a multi-layer structure is potential for the structure design of RRAM and an effective way to improve its performance.

Fig. 14. Typical DC I-V bipolar switching curves of oxide based synaptic devices. The multilevel states in this measurement are achieved by changing RESET stop voltages [120].

Fig. 15. Switching diagrams of ML I-V features: (a) I-V characteristics of switching of Pt/Ta2O5-x/TiOxNyconfiguration. (b) I-V curve of switching element of Pt/Ta2O5-x/TiN configuration. (c) Pt/Ta2O5-x/TiOxNy/TiN/Ta2O5-x/Pt matrix [124].

6. Challenges and Prospect

A basic overview of RRAM devices is given. Basic working principle and switching mechanism are summarized. There are other mechanisms in the same or different RS materials, which could not be totally covered in this review. Finally, we mainly discussed the effect of electrode materials and switching layer on the performance parameters.

In further pursuit of high speed and low power, researchers have become increasingly intrigued with RRAMs as a promising candidate for next generation non-volatile memory (NVM). Common parameters are used for monitoring the reliability of RRAM devices, such as retention time, cycling endurance, on-to-off ratio, and on-state current. From the perspective of technological application, several important issues should be also taken into consideration as follows. The first and foremost is scalability. With the switching cells down to the nanoscale, it is accompanied by inherent physical limits and technical barriers. The configuration and geometry of CFs in the host insulating matrix and thermal crosstalk between neighboring cells may play a critical role in RRAMs. Moreover, stability is thought to be not ignored. Generally, LRS and HRS of switching cells are not energetically stable, especially when switching cells are subjected in some specific conditions, like the severe stationary or the alternating stimulation, which will seriously affect the retention and endurance. Because the lifetime of CFs is a primary factor for the stability of RRAMs, it is essential to select proper switching and electrode materials.

The development of RRAM test chips until February 2014 is summarized in Table 3[102], which indicated the progress form primary reported programming/erasing properties to current product application. Although the development of RRAM has progressed rapidly in the last five years, there are still some unsolved issues and problems waiting for further study to be clearly elucidated. Questions involving the high power consumption, low endurance, and non-uniformity in the switching parameters are requiring further attention. Although the excellent performance in RRAMs was reported in some research, e.g. a retention time for over 10 years at a high-temperature measurement or a memory endurance of over 106 cycles, there is little information about characteristic variations from cell to cell and from chip to chip. Additionally, considering the different degree of operation stability for various resistive switching materials, the effect of defects in switching layers, and interface properties between the electrode and the switching layer, it is significant and necessary to make a deeper understanding of the switching mechanism from a microscopic point of view. A clear understanding of resistive switching mechanisms will contribute to explore the essence of resistive behavior, more importantly, which also has great significance on the improvement of performance parameters. More research efforts are also needed in the optimization of process and material as well as the improvement of fabrication technology. For further study, an important research direction is to find RS material systems with environment-friendly, compatibility with CMOS technology and excellent performance parameters. Based on the continuing work, we are convinced that resistive-switching RRAM devices will bring a breakthrough of technology and achieve success in future non-volatile memory application.

Table 3 RRAM test chips have been reported on famous international IC conference until 2014[31]
Acknowledgements Acknowledgments

The authors gratefully acknowledge the financial support from the National Natural Science Foundation of China (Nos. 61474039 and 51572002), and the Nature Science Foundation (Key Project) of Hubei Province (No. 2015CFA052).

The authors have declared that no competing interests exist.

Reference
[1] T. W. HickmottAppl. Phys. Lett, 33(1962), pp. 2669-2682 [本文引用:1]
[2] P. D. Greene, E. L. Bush, I. R. RawlingsF. Vrátny (Ed. ), Proceedings of the Symposium on Deposited Thin Film Dielectric Materials, Electrochemical Society, New York (1968), pp. 167-185 [本文引用:1]
[3] R. R. Sutherland J. Phys. D Appl. Phys, 4(1971), pp. 468-479 [本文引用:1]
[4] G. Dearnaley, D. V. Morgan, A. M. Stoneham J. Non Cryst. Solids, 4(1970), pp. 593-612 [本文引用:1]
[5] T. W. Hickermott Appl. Phys. Lett, 33(1962), pp. 2669-2682 [本文引用:1]
[6] J. G. Simmons, R. R. Verderber Proc. R. Soc. A, 301(1967), pp. 77-102 [本文引用:1]
[7] K. Kahng, S. M. Sze Bell Syst. Tech. J. , 46(1967), pp. 1288-1295 [本文引用:1]
[8] F. Masuoka, M. Asano, H. Iwahashi, T. Komuro, S. Tanaka IEEE Electron Devices Meeting, vol. 30(1984), pp. 464-467 [本文引用:1]
[9] A. Chen, S. Haddad, Y. C. Wu, T. N. Fang, Z. Lan, S. Avanzino, S. Pangrle, M. Buynoski, M. Rathor, W. Cai, N. Tripsas, C. Bill, M. VanBuskirk, M. . Taguchi IEEE Electron Devices Meeting(2005), pp. 746-749 [本文引用:1]
[10] B. O. Cho, T. Yasue, H. Yoon, M. S. Lee, I. S. Yeo, U. I. Chung, J. T. Moon, B. I. Ryu IEEE Electron Devices Meeting(2006), pp. 1-4 [本文引用:1]
[11] Y. S. Lai, C. H. Tu, D. L. Kwong, J. S. Chen IEEE Electron Device Lett, 27(2006), pp. 451-453 [本文引用:1]
[12] D. Lee, D. J. Seong, H. J. Choi, I. Jo, R. Dong, W. Xiang, S. Oh, P. Myeongbum, S. O. Seo, S. Heo, M. Jo, D. K. Hwang, H. K. Park, M. Chang, M. Hasan, H. Hwang IEEE Electron Devices Meeting(2006), pp. 797-800 [本文引用:1]
[13] R. Waser, M. AonoNat. Mater, 6(2007), pp. 833-840 [本文引用:1]
[14] K. Tsunoda, K. Kinoshita, H. Noshiro, Y. Yamazaki, T. Iizuka, Y. Ito, A. Takahashi, A. Okano, Y. Sato, T. Fukano, M. Aoki, Y. Sugiyama IEEE Electron Devices Meeting(2007), pp. 767-770 [本文引用:1]
[15] C. Schindler, S. C. P. Thermadam, R. Waser, M. N. Kozicki IEEE Trans. Electron Devices, 54(2007), pp. 2762-2768 [本文引用:1]
[16] W. Guan, S. Long, Q. Liu, M. Liu, W. Wang IEEE Electron Device Lett, 29(2008), pp. 434-436 [本文引用:1]
[17] Y. Li, Y. Zhong, L. Xu, J. Zhang, X. Xu, H. Sun, X. Miao Sci. Rep, 3(2013), p. 1619 [本文引用:1]
[18] K. I. Chou, C. H. Cheng, Z. W. Zheng, M. Liu, A. Chin IEEE Electron Device Lett, 34(2013), pp. 505-507 [本文引用:1]
[19] Y. C. Yang, F. Pan, Q. Liu, M. Liu, F. Zeng Nano Lett, 9(2009), pp. 1636-1643 [本文引用:3]
[20] P. Huang, Y. J. Wang, H. T. Li, B. Gao, B. Chen, F. F. Zhang, L. Zeng, G. Du, J. F. Kang, X. Y. Liu IEEE Nanotechnol, 13(2014), pp. 1127-1132 [本文引用:1]
[21] W. Y. Chang, J. H. Liao, Y. S. Lo, T. B. Wu Appl. Phys. Lett, 94(2009), p. 2107 [本文引用:1]
[22] W. L. Bai, R. Huang, Y. M. Cai, Y. Tang, X. Zhang, Y. Y. Wang IEEE Electron Device Lett, 34(2013), pp. 223-225 [本文引用:1]
[23] S. Seo, M. J. Lee, D. H. Seo, E. J. Jeoung, D. S. Suh, Y. S. Joung Appl. Phys. Lett, 85(2004), pp. 5655-5657 [本文引用:1]
[24] G. Ma, X. Tang, H. Su, Y. Li, H. Zhang, Z. Zhong IEEE Electron Devices, 61(2014), pp. 1237-1240 [本文引用:1]
[25] M. J. Lee, S. Seo, D. C. Kim, S. E. Ahn, D. H. Seo, I. K. Yoo, I. G. Baek, D. S. Kim, I. S. Byun, S. H. Kim, I. R. Hwang, J. S. Kim, S. H. Jeon, B. H. Park Adv. Mater, 19(2007), pp. 73-76 [本文引用:1]
[26] U. Russo, D. Jelmini, C. Cagli, A. L. Lacaita, S. Spiga, C. Wiemer, M. Fanciulli IEEE Electron Devices Meeting(2007), pp. 775-778 [本文引用:2]
[27] D. H. Kwon, K. M. Kim, J. H. Jang, J. M. Jeon, M. H. Lee, G. H. Kim, X. S. Li, G. S. Park, B. Lee, S. Han, M. Kim, C. S. Hwang Nat. Nanotechnol, 5(2010), pp. 148-153 [本文引用:1]
[28] S. C. Chae, J. S. Lee, S. Kim, S. B. Lee, S. H. Chang, C. Liu, B. Kahng, H. Shin, D. W. Kim, C. U. Jung, S. Seo, M. J. Lee, T. W. Noh Appl. Phys. Lett, 95(2009), p. 093508 [本文引用:1]
[29] R. Mohammadpour, A. Irajizad, N. Taghavinia, M. Rahman, M. M. Ahadian J. Mater. Sci. Technol, 26(2008), pp. 535-541 [本文引用:1]
[30] S. S. Batool, Z. Imran, M. Israr Qadir, M. Usman, H. Jamil, M. A. Rafiq, M. M. Hassan, M. Willand er J. Mater. Sci. Technol, 29(2013), pp. 411-414 [本文引用:1]
[31] W. W. He, C. H. Ye J. Mater. Sci. Technol, 31(2015), pp. 281-588 [本文引用:1]
[32] T. L. Tsai, Y. H. Lin, T. Y. Tseng IEEE Electron Device Lett, 36(2015), pp. 366-368 [本文引用:1]
[33] Q. Zuo, S. Long, S. Yang, Q. Liu, L. Shao, Q. Wang, S. Zhang, Y. Li, Y. Wang, M. Liu IEEE Electron Device Lett, 31(2010), pp. 344-346 [本文引用:1]
[34] X. A. Tran, W. Zhu, W. J. Liu, Y. C. Yeo, B. Y. Nguyen, H. Y. Yu IEEE Electron Device Lett, 33(2012), pp. 1402-1404 [本文引用:1]
[35] F. Yuan, Z. Zhang, J. C. Wang, L. Pan, J. Xu, C. S. Lai Nanoscale Res. Lett, 91(2014), pp. 1-6 [本文引用:1]
[36] Q. Zhou, J. Zhai Appl. Surf. Sci, 284(2013), pp. 644-650 [本文引用:1]
[37] C. Ye, T. F. Deng, J. J. Wu, C. Zhan, H. Wang, J. Zhang Jpn J. Appl. Phys, 54(2015), p. 054201 [本文引用:1]
[38] H. S. P. Wong, H. Y. Lee, S. Yu, Y. S. Chen, Y. Wu, P. S. Chen, B. Lee, F. T. Chen, M. J. Tsai Proc. IEEE, 100(2012), pp. 1951-1970 [本文引用:3]
[39] B. Govoreanu, G. S. Kar, Y. Y. Chen, V. Paraschiv, S. Kubicek, A. Fantini, I. P. Radu, L. Goux, S. Clima, R. Degraeve, N. Jossart, O. Richard, T. Vand eweyer, K. Seo, P. Hendrickx, G. Pourtios, H. Bender, L. Altimime, D. J. Wouters, J. A. Kittl, M. Jurczak IEEE Electron Devices Meeting, vol. 31(2011), pp. 1-4 [本文引用:1]
[40] Y. Sasago, M. Kinoshita, T. Morikawa, K. Kurotsuchi, S. Hanzawa, T. Mine, A. Shima, Y. Fujisaki, H. Kume, H. Moriya, N. Takaura, K. Torii Symposium on IEEE, VLSI Technology(2009), pp. 24-25 [本文引用:1]
[41] G. He, Z. Q. Sun, M. Liu, L. D. Zhang Appl. Phys. Lett, 97(2010), p. 192902 [本文引用:1]
[42] W. Y. Chang, Y. C. Lai, T. B. Wu, S. F. Wang, F. Chen, M. J. Tsai Appl. Phys. Lett, 92(2008), p. 022110 [本文引用:2]
[43] Y. Wang, W. Tang, L. Zhang J. Mater. Sci. Technol, 31(2015), pp. 175-181 [本文引用:1]
[44] Y. Wu, D. Liu, N. Yu, Y. Liu, H. Liang, G. Du J. Mater. Sci. Technol, 29(2013), pp. 830-834 [本文引用:1]
[45] W. C. Chien, Y. C. Chen, F. M. Lee, Y. Y. Lin, E. K. Lai, Y. D. Yao, C. Y. Lu Jpn J. Appl. Phys, 50 (2011), p. 04DD11 [本文引用:1]
[46] H. Y. Lee, P. S. Chen, T. Y. Wu, Y. S. Chen, C. C. Wang, P. J. Tzeng, C. H. Lin, F. Chen, C. H. Lien, M. J. Tsai IEEE International Electron Devices Meeting (IEDM)(2008), pp. 1-4 [本文引用:4]
[47] M. J. Lee, C. B. Lee, D. Lee, S. R. Lee, M. Chang, J. H. Hur, Y. B. Kim, C. J. Kim, D. H. Seo, S. Seo, U. I. Chung, I. K. Yoo, K. Kim Nat. Mater, 10(2011), pp. 625-630 [本文引用:1]
[48] C. Ye, C. Zhan, T. M. Tsai, K. C. Chang, M. C. Chen, T. C. Chang, T. F. Deng, H. Wang Appl. Phys. Express, 7(2014), p. 034101 [本文引用:2]
[49] C. Chen, Y. C. Yang, F. Zeng, F. Pan, Z. S. Wang, J. Yang Prog. Nat. Sci, 20(2010), pp. 1-15 [本文引用:1]
[50] S. Seo, M. J. Lee, D. H. Seo, E. J. Jeoung, D. S. Suh, Y. S. Joung, I. K. Yoo, I. R. Hwang, S. H. Kim, I. S. Byun, J. S. Kim, J. S. Choi, B. H. Park Appl. Phys. Lett, 85(2004), p. 5655 [本文引用:1]
[51] C. Rohde, B. J. Choi, D. S. Jeong, S. Choi, J. S. Zhao, C. S. Hwang Appl. Phys. Lett, 86(2005), p. 262907 [本文引用:1]
[52] C. Y. Lin, C. Y. Wu, C. Y. Wu, T. C. Lee, F. L. Yang, C. Hu, T. Y. Tseng IEEE Electron Device Lett, 28(2007), pp. 366-368 [本文引用:5]
[53] Y. M. Kim, J. S. Lee J. Appl. Phys, 104(2008), p. 114115 [本文引用:1]
[54] J. S. Choi, J. S. Kim, I. R. Hwang, S. H. Hong, S. H. Jeon, S. -O. Kang, B. H. Park, D. C. Kim, M. J. Lee, S. Seo Appl. Phys. Lett, 95(2009), p. 022109 [本文引用:1]
[55] C. Yoshida, K. Tsunoda, H. Noshiro, Y. Sugiyama Appl. Phys. Lett, 91(2007), p. 223510 [本文引用:1]
[56] N. Xu, L. F. Liu, X. Sun, C. Chen, Y. Wang, D. D. Han, X. Y. Liu, R. Q. Han, J. F. Kang, B. Yu Semicond. Sci. Technol, 23(2008), p. 075019 [本文引用:1]
[57] L. Goux, Y. Y. Chen, L. Pantisano, X. P. Wang, G. Groeseneken, M. Jurczak, D. J. Wouters Electrochem. Solid-State Lett, 13(2010), pp. G54-G56 [本文引用:1]
[58] B. Gao, S. Yu, N. Xu, L. F. Liu, B. Sun, X. Y. Liu, R. Q. Han, J. F. Kang, B. Yu, Y. Y. Wang IEEE International Electron Devices Meeting (IEDM)(2008), pp. 1-4 [本文引用:1]
[59] S. Yu, H. S. P. Wong IEEE Electron Device Lett, 31(2010), pp. 1455-1457 [本文引用:1]
[60] U. Russo, D. Ielmini, C. Cagli, A. L. Lacaita IEEE Trans. Electron Devices, 56(2009), pp. 186-192 [本文引用:1]
[61] U. Russo, D. Ielmini, C. Cagli, A. L. Lacaita IEEE Trans. Electron Devices, 56(2009), pp. 193-199 [本文引用:1]
[62] C. Cagli, F. Nardi, D. Ielmini IEEE Trans. Electron Devices, 56(2009), pp. 1712-1720 [本文引用:1]
[63] S. M. Yu, B. Lee, H. S. P. Wong Functional Metal Oxide Nanostructures Springer Series in Materials Science, vol. 149, Springer (2012) [本文引用:2]
[64] D. S. Jeong, B. J. Choi, C. S. Hwang J. Appl. Phys, 100(2006), p. 113724 [本文引用:1]
[65] Q. G. Zhou, J. W. Zhai Appl. Surf. Sci, 284(2013), pp. 644-650 [本文引用:2]
[66] F. Pan, C. Chen, Z. S. Wang, Y. C. Yang, J. Yang, F. Zeng Prog. Nat. Sci. Mater. Int, 20(2010), pp. 1-15 [本文引用:1]
[67] C. Schindler, G. Staikov, R. Waser Appl. Phys. Lett, 94(2009), p. 072109 [本文引用:1]
[68] M. N. Kozicki, M. Park, M. Mitkova IEEE Trans. Nanotechnol, 4(2005), pp. 331-338 [本文引用:1]
[69] Y. Hirose, H. Hirose J. Appl. Phys, 47(1976), pp. 2767-2772 [本文引用:1]
[70] T. Fujii, M. Arita, Y. Takahashi, I. Fujiwara Appl. Phys. Lett, 98(2011), p. 212104 [本文引用:1]
[71] B. Sun, H. Li, L. Wei, P. Chen Cryst Eng Comm, 16(2014), pp. 9891-9895 [本文引用:1]
[72] J. Billen, S. Streudel, R. Müller, J. Genoe, P. Heremans Appl. Phys. Lett, 91(2007), p. 263507 [本文引用:1]
[73] T. Kever, U. Boettger, C. Schindler, R. Waser Appl. Phys. Lett, 91(2007), p. 083506 [本文引用:1]
[74] K. Szot, W. Speier, G. Bihlmayer, R. Waser Nat. Mater, 5(2006), pp. 312-320 [本文引用:1]
[75] Y. T. Li, S. B. Long, H. B. Lv, Q. Liu, Q. Wang, Y. Wang, S. Zhang, W. T. Lian, S. Liu, M. Liu Chin. Phys. B, 20(2011), p. 017305 [本文引用:1]
[76] C. B. Lee, B. S. Kang, A. Benayad, M. J. Lee, S. E. Ahn, K. H. Kim, G. Stefanovich, Y. Park, I. K. Yoo Appl. Phys. Lett, 93(2008), p. 042115 [本文引用:1]
[77] Y. T. Li The study of binary metal oxide based resistive switching memory Lanzhou University (2011) in Chinese [本文引用:1]
[78] S. Seo, M. J. Lee, D. C. Kim, S. E. Ahn, B. H. Park, Y. S. Kim, I. K. Yoo, I. S. Byon, I. R. Hwang, J. S. Kim, J. S. Choi, J. H. Lee, S. H. Jeon, S. H. Hong, B. H. Park Appl. Phys. Lett, 87(2005), p. 263507 [本文引用:1]
[79] S. Seo, M. J. Lee, D. H. Seo, E. J. Jeoung, D. S. Suh, Y. S. Joung, I. K. Yoo, I. R. Hwang, S. H. Kim, I. S. Byun, J. S. Kim, J. S. Choi, B. H. Park Appl. Phys. Lett, 85(2004), pp. 5655-5657 [本文引用:1]
[80] W. Y. Yang, S. W. Rhee Appl. Phys. Lett, 91(2007), p. 232907 [本文引用:1]
[81] S. T. Hsu, W. Pan, F. Zhang, W. W. Zhuang, T. Li, U. S. Patent, No. 6, 849, 891, 2005. [本文引用:1]
[82] Y. Fukuda, K. Aoki, A. Nishimura, K. Numata, U. S. Patent Washington, No. 5, 508, 953, 1996. [本文引用:1]
[83] L. E. Yu, S. Kim, M. K. Ryu, S. Y. Choi, Y. K. Choi IEEE Electron Device Lett, 29(2008), pp. 331-333 [本文引用:1]
[84] C. H. Cheng, A. Chin, F. S. Yeh IEEE Electron Device Lett, 32(2011), pp. 366-368 [本文引用:1]
[85] Y. Chai, Y. Wu, K. Takei, H. Y. Chen, S. Yu, P. C. Chan, H. S. P. Wong IEEE Trans. Electron Devices, 58(2011), pp. 3933-3939 [本文引用:1]
[86] Q. Zuo, S. Long, S. Yang, Q. Liu, L. Shao, Q. Wang, M. Liu IEEE Electron Device Lett, 31(2010), pp. 344-346 [本文引用:2]
[87] H. Tian, H. Y. Chen, B. Gao, S. Yu, J. Liang, Y. Yang, X. Dan, J. F. Kang, T. J. Ren, Y. G. Zhang, H. S. P. Wong Nano Lett, 13(2013), pp. 651-657 [本文引用:1]
[88] S. Kwon, H. Seo, H. Lee, K. J. Jeon, J. Y. Park Appl. Phys. Lett, 100(2012), p. 123101 [本文引用:1]
[89] H. Y. Lee, P. S. Che, T. Y. Wu, Y. S. Che, C. C. Wan, P. J. Tzen, M. J. Tsai IEEE International Electron Devices Meeting (IEDM)(2008), pp. 1-4 [本文引用:1]
[90] B. Govoreanu, G. S. Kar, Y. Y. Chen, V. Paraschiv, S. Kubicek, A. Fantini, M. Jurczak IEEE International Electron Devices Meeting (IEDM), vol. 31(2011), pp. 1-4 [本文引用:1]
[91] H. Y. Lee, P. S. Chen, T. Y. Wu, Y. S. Chen, F. Chen, C. C. Wang, C. Lien IEEE Electron Device Lett, 30 (2009), pp. 703-705 [本文引用:1]
[92] S. Y. Wang, D. Y. Lee, T. Y. Tseng, C. Y. Lin Appl. Phys. Lett, 95 (2009), p. 112904 [本文引用:1]
[93] K. C. Liu, W. H. Tzeng, K. M. Chang, Y. C. Chan, C. C. Kuo, C. W. Cheng Microelectron. Reliab, 50(2010), pp. 670-673 [本文引用:1]
[94] S. C. Chen, T. C. Chang, S. Y. Chen, C. W. Chen, S. C. Chen, S. M. Sze, M. J. Tasi, M. J. Kao, F. S. Y. Huang Solid State Electron, 62(2011), pp. 40-43 [本文引用:1]
[95] H. Lv, M. Wang, H. Wan, Y. Song, W. Luo, P. Zhou, M. H. Chi Appl. Phys. Lett, 94(2009), p. 213502 [本文引用:1]
[96] X. Zhu, W. Su, Y. Liu, B. Hu, L. Pan, W. Lu, R. W. Li Adv. Mater, 24(2012), pp. 3941-3946 [本文引用:1]
[97] B. Hu, F. Zhuge, X. Zhu, S. Peng, X. Chen, L. Pan, R. W. Li J. Mater. Chem, 22(2012), pp. 520-526 [本文引用:1]
[98] H. S. P. Wong, H. Y. Lee, S. M. Yu, Y. S. Chen, Y. Wu, P. S. Chen, B. Lee, T. C. Frederick, M. J. Tsai Proc. IEEE, 100(2012), pp. 1951-1970 [本文引用:2]
[99] B. Govoreanu, G. S. Kar, Y. Y. Chen, V. Paraschiv, S. Kubicek, A. Fantini, M. Jurczak IEDM Electron Devices Meeting IEEE, vol. 31(2011), pp. 1-4 [本文引用:1]
[100] Y. Sasago, M. Kinoshita, T. Morikawa, K. Kurotsuchi, S. Hanzawa, T. Mine, K. Torii, H. Kume, K. Torii, H. Moriya IEEE VLSI Technology(2009), pp. 24-25 [本文引用:1]
[101] X. A. Tran, W. Zhu, W. J. Liu, Y. C. Yeo, B. Y. Nguyen, Y. Y. Hong IEEE Electron Device Lett, 33(2012), pp. 1402-1404 [本文引用:1]
[102] ITRS (International Technology Roadmap for Semiconductors) http://www.itrs.net(2008 [本文引用:3]
[103] D. Lee, D. J. Seong, I. Jo, R. Dong, W. Xiang, H. Hwang IEDM Electron Devices Meeting IEEE(2006), pp. 1-4 [本文引用:1]
[104] K. Tsunoda, K. Kinoshita, H. Noshiro, Y. Yamazaki, T. Iizuka, Y. Ito, Y. Sugiyama IEDM Electron Devices Meeting IEEE(2007), pp. 767-770 [本文引用:1]
[105] Z. Wang, W. G. Zhu, A. Y. Du, L. Wu, Z. Fang, X. A. Tran, H. Y. Yu IEEE Electron Device Lett, 59(2012), pp. 1203-1208 [本文引用:1]
[106] Y. Wang, Q. Liu, S. Long, W. Wang, Q. Wang, M. Zhang, M. Liu Nanotechnology, 21(2010), p. 045202 [本文引用:1]
[107] T. Y. Li, S. B. Long, H. B. Lu, Q. Liu, S. Liu, M. Liu Chin. Sci. Bull, 56 (2011), pp. 1967-1973 in Chinese [本文引用:1]
[108] R. Waser, R. Dittmann, G. Staikov, K. Szot Adv. Mater, 21(2009), pp. 2632-2663 [本文引用:1]
[109] Y. Li, S. Long, Q. Liu, H. , S. Liu, M. Liu Chin. Sci. Bull, 56(2011), pp. 3072-3078 [本文引用:1]
[110] Z. X. Chen, Z. Fang, Y. Wang J. Electron. Mater, 43(2014), pp. 4193-4198 [本文引用:1]
[111] G. H. Kim, J. H. Lee, J. Y. Seok, S. J. Song, J. H. Yoon, K. J. Yoon, C. S. Hwang Appl. Phys. Lett, 98(2011), p. 262901 [本文引用:1]
[112] J. Lee, E. M. Bourim, W. Lee, J. Park, M. Jo, S. Jung, H. H wang Appl. Phys. Lett, 97(2010), p. 172105 [本文引用:1]
[113] Y. L. Song, Y. Liu, Y. L. Wang, X. P. Tian, L. M. Yang, Y. Y. Lin IEEE Electron Device Lett, 32(2011), pp. 1439-1441 [本文引用:1]
[114] S. G. Park, M. K. Yang, H. Ju, D. J. Seong, J. M. Lee, E. Kim, C. Chung IEEE In Electron Devices Meeting (IEDM)(2012), pp. 1-4 [本文引用:1]
[115] J. Yoon, H. Choi, D. Lee, J. B. Park, J. Lee, D. J. Seong, H. H wang IEEE Electron Device Lett, 30(2009), pp. 457-459 [本文引用:1]
[116] Y. Bai, H. Wu, Y. Zhang, M. Wu, J. Zhang, N. Deng, Z. Yu Appl. Phys. Lett, 10(2013), p. 173503 [本文引用:1]
[117] S. M. Yu, Y. Wu, Y. Chai, J. Provine, W. Philip IEEE VLSI-TSA, 11 (2010), p. 94305 [本文引用:1]
[118] G. Bin, H. B. Dai, B. Sun, L. F. Liu, X. Y. Liu, R. Q. Han, J. F. Kang, B. Yu Electronchem. Solid State Lett, 12(2010), p. H36 [本文引用:1]
[119] Z. Fang, H. Y. Yu, X. Li, N. Singh, G. Q. Lo, D. L. Kwong IEEE International Electron Devices Meeting (IEDM), vol. 28(2011), pp. 1-4 [本文引用:1]
[120] S. Yu, B. Gao, Z. Fang, H. Y. Yu, J. F. Kang, H. S. P. Wong Adv. Mater, 25(2013), pp. 1774-1779 [本文引用:1]
[121] I. G. Baek, D. C. Kim, M. J. Lee, H. J. Kim, E. K. Yim, M. S. Lee, J. E. Lee, S. E. Ahn, S. Seo, J. H. Lee, J. C. Park, Y. K. Cha, S. O. Park, H. S. Kim, I. K. Yoo, U. I. Chung, J. T. Moon, B. I. Ryu Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International(2005), pp. 750-753 [本文引用:1]
[122] G. S. Snider IEEE International Symposium on Nanoscale Architectures(NANOARCH)(2008), pp. 85-92 [本文引用:1]
[123] M. Suri, O. Bichler, D. Querlioz, O. Cuet, L. Perniola, V. Sousa, D. Vuillaume, C. Gamrat, B. DeSalvo IEEE International Electron Devices Meeting (IEDM), vol. 4 (2011), pp. 1-4 [本文引用:1]
[124] A. R. Lee, Y. C. Bae, G. H. Baek, H. S. Im, J. P. Hong Appl. Phys. Lett, 103(2013), p. 063505 [本文引用:1]
[125] R. Fackenthal, M. Kitagawa, W. Otsuka, K. Prall, D. Mills, K. Tsutsui, J. Javanifard, K. Tedrow, T. Tsushima, Y. Shibahara, G. Hush IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC)(2014), pp. 338-339 [本文引用:1]
[126] M. F. Chang, J. J. Wu, T. F. Chien, Y. C. Liu, T. C. Yang, W. C. Shen, Y. C. King, C. J. Lin, K. F. Lin, Y. D. Chih, S. Natarajan, J. Chang IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC)(2014), pp. 332-333 [本文引用:1]
[127] M. F. Chang, C. C. Kuo, S. S. Sheu, C. J. Lin, Y. C. King, Z. H. Lin, K. L. Su, Y. S. Chen, W. P. Lin, H. Y. Lee, C. H. Tsai, W. S. Chen, F. T. Chen, T. K. Ku, M. J. Kao, M. J. Tsai, J. J. Wu, Y. D. Chih, S. Natarajan Symposium on VLSI Circuits (VLSIC)(2013), pp. C112-C113 [本文引用:1]
[128] Y. L. Song, Y. Meng, X. Y. Xue, F. J. Xiao, Y. Liu, B. Chen, Y. Y. Lin, Q. T. Zou, R. Huang, J. G. Wu Symposium on VLSI Technology (VLSIT)(2013), pp. T102-T103 [本文引用:1]
[129] A. Kawahara, K. Kawai, Y. Ikeda, Y. Katoh, R. Azuma, Y. Yoshimoto, K. Tanabe, W. Z. Qiang, T. Ninomiya, K. Katayama, R. Yasuhara, S. Muraoka, A. Himeno, N. Yoshikawa, H. Murase, K. Shimakawa, T. Takagi, T. Mikawa, K. Aono IEEE International Solid-State Circuits Conference Digest of Technical Papers(ISSCC)(2013), pp. 220-221 [本文引用:1]
[130] T. Y. Liu, T. H. Yan, R. Scheuerlein, Y. C. Chen, J. K. Lee, G. Balakrishnan, G. Yee, H. Zhang, A. Yap, J. Ouyang, T. Sasaki, A. Al-Shamma, C. Chen, M. Gupta, G. Hilton, A. Kathuria, V. Lai, M. Matsumoto, A. Nigam, A. Pai, J. Pakhale, H. S. Chang, X. X. Wu, Y. Yin, N. Nagel, Y. Tanaka, M. Higashitani, T. Minvielle, C. Gorla, T. Tsukamoto, T. Yamaguchi, M. O. Kajima, T. O. Kamura, S. Takase, H. Inoue, L. Fasoli IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC)(2013), pp. 210-220 [本文引用:1]
[131] X. Y. Xue, W. X. Jian, J. G. Yang, F. J. Xiao, G. Chen, X. L. Xu, Y. F. Xie, Y. Y. Lin, R. Huang, Q. T. Zhou, J. G. Wu Symposium on VLSI Circuits (VLSIC)(2012), pp. 42-43 [本文引用:1]
[132] M. F. Chang, C. W. Wu, C. C. Kuo, S. J. Shen, K. F. Lin, S. M. Yang, Y. C. King, C. J. Lin, Y. D. Chih IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC)(2012), pp. 434-436 [本文引用:1]
[133] A. Kawahara, R. Azuma, Y. Ikeda, K. Kawai, Y. Katoh, K. Tanabe, T. Nakamura, Y. Sumimoto, N. Yamada, N. Nakai, S. Sakamoto, Y. Hayakawa, K. Tsuji, S. Yoneda, A. Himeno, K. Origasa, K. Shimakawa, T. Takagi, T. Mikawa, K. Aono IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC)(2012), pp. 432-433 [本文引用:1]
[134] S. Hollmer, N. Gilbert, J. Dinh IEEE International Memory Workshop (IMW)(2011), pp. 107-110 [本文引用:1]
[135] S. S. Sheu, M. F. Chang, K. F. Lin, C. W. Wu, Y. S. Chen, P. F. Chiu, C. C. Kuo, Y. S. Yang, P. C. Chiang, W. P. Lin, C. H. Lin, H. Y. Lee, P. Y. Gu, S. M. Wang, F. T. Chen, K. L. Su, C. H. Lien, K. H. Cheng, H. T. Wu, T. K. Ku, M. J. Kao, M. J. Tsai IEEE International Solid-State Circuits Conference (ISSCC)(2011), pp. 200-202 [本文引用:1]
[136] W. Otsuka, K. Miyata, M. Kitagawa, K. Tsutsui, T. Tsushima, H. Yoshihara, T. Namise, Y. Terao, K. Ogata IEEE International Solid-State Circuits Conference (ISSCC)(2011), pp. 210-211 [本文引用:1]
[137] M. Wang, W. J. Luo, Y. L. Wang, L. M. Yang, W. Zhu, P. Zhou, J. H. Yang, X. G. Gong, Y. Y. Lin, R. Huang, S. Song, Q. T. Zhou, H. M. Wu, J. G. Wu, M. H . Chi Symposium on VLSI Technology(VLSIT)(2010), pp. 89-90 [本文引用:1]
[138] C. J. Chevallier, H. S. Chang, S. F. Lim, S. R. Namala, M. Matsuoka, B. L. Bateman, D. Rinerson IEEE International Solid-State Circuits Conference (ISSCC)(2010), pp. 260-261 [本文引用:1]
[139] H. Honigschmid, M. Angerbauer, S. Dietrich, M. Dimitrova, D. Gogl, C. Liaw, M. Markert, R. Symanczyk, L. Altimime, S. Bournat, G. Muller Symposium on VLSI Circuits (VLSIC) (2006), pp. 110-111 [本文引用:1]