Abstract: Tunnel junctions, Ta (5 nm)/Ni79Fe21 (3 nm)/Cu (20 nm)/Ni79Fe21 (3 nm)/lr(22)Mn(78) (10 nm)/Co75Fe25 (4 nm)/Al (d nm)-oxide/Co75Fe25 (4 nm)/Ni79Fe21 (20 nm)/Ta(5 nm) wherein d=1.3 and 0.8 nm, with small active area from 100x100 down to 3x3 mum(2) were fabricated using a micro-fabrication technique. The optical lithography combined with Ar ion-beam etching and CF4 active etching was used to pattern the junction area. A thin barrier layer and a short plasma-oxidation time for At-oxide layer were used in order to reduce the junction resistance and increase the TMR ratio. The optimum annealing temperature and time for the highest TMR obtained were investigated to be around 300℃ for an hour in this work. TMR ratio, effective barrier height and width, and breakdown voltage of the junctions can be remarkably enhanced upon annealing. High TMR ratio of 49.7% at room temperature and 69.1% at 4.2 K were achieved. TMR ratio and resistances decrease with increasing de bias voltage from 0 to 1000 mV or with increasing temperature from 4.2 K to room temperature.

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