Fig. 1. Fabrication process and schematic illustration of the device structure. (a) Photograph of a two-inch sapphire wafer uniformly covered by monolayer MoS2 film grown by CVD. (b-f) A brief fabrication process of MoS2 to gated FETs employing metal gates with different work functions. (g) Schematic cross-section of the MoS2-based FET. (h) Optical microscopy image of the MoS2 TG-FET array on a diced 1 cm × 1 cm wafer. The scale bar is 200 μm.

Fig. 2. Transfer characteristics of MoS2 FETs with different metal TG electrodes. (a) Transfer curves (VD = 0.2 V) of the transistors in linear scale (left Y-axis) and logarithmic scale (right Y-axis) with Au (5.1 eV), Cu (4.65 eV), Ag (4.3 eV), and Al (4.08 eV) gates, respectively. (b) Statistical result of the Vth of MoS2 FETs with four different metal gates (30 random samples for each type of metal). (c) Average Vth versus metal gate work function.

Fig. 3. Characterization of the dipole effect induced in MoS2-based FETs with Al gates. (a) Cross-sectional HRTEM image of the Al gate region. (b) Zoom-in of the Al/HfO2 interface, which confirms the oxidation of the Al gate at the interface. (c) Cross-sectional HAADF image and the corresponding EDS element mappings of the Al/HfO2 interface. (d) Schematic illustration of the dipole due to Vo for the Al2O3/HfO2/SL/MoS2 stack structure. (e) Vertical schematic flat-band diagrams of the MoS2 transistors with Al, Ag, and Au gates at zero gate bias. For metal gates with different work functions, the channel is under either accumulation or depletion regions. Furthermore, the band diagram of those with Al gates indicates the dipole effect occurring in the gate dielectric layer.

Fig. 4. Electrical characterization of the MoS2-based inverter. (a) Schematic diagram of the inverter circuit configuration in cross-section and the corresponding electrical measurement setup. (b) Optical microscopy image of the inverter. Scale bar is 30 μm. (c) Transfer curves of the load and driver MoS2-based FETs in linear scale (left Y-axis) and logarithmic scale (right Y-axis). The load transistor has an Al gate, whereas the driver transistor has an Au gate. The difference between the work function of Al and Au results in a 0.75 V shift in Vth. (d) Output characteristics of the driver transistor with Au gate (the purple curves) and the load characteristic of the load transistor with Al gate (the red curve).

Fig. 5. Characteristics of the MoS2-based inverter. (a) Voltage transfer characteristic of the inverter (purple curve) and the corresponding voltage gain (red curve). Inset is the circuit diagram of the inverter. (b) Bi-stable hysteresis voltage transfer characteristics of the inverter. VOH represents the minimum high output voltage when the output level is logic “1”; VOL represents the maximum low output voltage when the output level is logic “0”; VIL represents the maximum low input voltage, which can be interpreted as logic “0”; and VIH represents the minimum high input voltage, which can be interpreted as logic “1”. (c) The distribution of the voltage transfer characteristics of the inverter. Inset shows the histogram of the VM shift and the Gaussian fit for 30 MoS2-based inverters based on the statistical database. (d) Relationship between average VM and work function of the load transistor metal gates (Au, Cu, Ag, and Al). The MoS2-based inverters composed of load transistor with W/L = 30 μm/20 μm (black dots) and W/L = 225 μm/15 μm (red dots) are further compared. All the driver transistors have the same Au gate and the identical W/L of 30 μm/20 μm.